1. Field of the Invention
The present invention relates to electroluminescent display matrix screens formed of a set of light-emitting diodes. Such screens are for example formed of organic diodes (“OLED”, for Organic Light Emitting Display) or polymer diodes (“PLED” for Polymer Light Emitting Display). The present invention more specifically relates to the regulation of the supply voltage of the control circuits of the light-emitting diodes of such screens.
2. Discussion of the Related Art
FIG. 1 shows a matrix screen comprised of n columns C1 to Cn and k lines L1 to Lk enabling addressing n*k light-emitting diodes d having their anodes connected to a column and their cathodes connected to a line.
Line control circuits CL1 to CLk enable respectively biasing lines L1 to Lk. A single line is activated at a time and is biased to ground. The non-activated lines are biased to a voltage Vligne.
Column control circuits CC1 to CCn enable respectively biasing columns C1 to Cn. The columns addressing the light-emitting diodes which are desired to be activated are biased by a current to a voltage VCOL greater than the threshold voltage of the screen light-emitting diodes. The columns which are not desired to be activated are grounded.
A light-emitting diode connected to the activated line and to a column biased to VCOL is then on and emits light. Voltage Vligne is provided to be high enough for the light-emitting diodes connected to the non-activated lines and to the columns at voltage VCOL not to be on and to emit no light.
FIG. 2 shows a conventional example of a column control circuit CC and of a line control circuit CL respectively addressing a column C and a line L connected to a light-emitting diode d of the screen. Line control circuit CL comprises a power inverter 1 controlled by a line control signal φL. Power inverter 1 comprises an NMOS transistor 2 enabling discharging line L when φL is high and a PMOS transistor 3 enabling charging line L to bias voltage Vligne when φL is low.
Column control circuit CC comprises a current mirror formed in the present example with two PMOS-type transistors 4, 5. Transistor 4 forms the reference branch of the mirror and transistor 5 forms the duplication terminal. The sources of transistors 4 and 5 are connected to a bias voltage VPOL on the order of 15 V for OLED screens. The gates of transistors 4 and 5 are interconnected. The drain and the gate of transistor 4 are interconnected. Transistor 4 is thus diode-connected, the source-gate voltage (Vsg4) being equal to the source-drain voltage (Vsd4). The drain of transistor 4 is connected to the source of a PMOS-type power transistor 6. The drain and the gate of transistor 6 are interconnected. The drain of transistor 6 is connected to a terminal of a current source 7 having its other terminal connected to ground GND. The current flowing through transistor 4 is set by current source 7 which provides a so-called “luminance” current ILUM.
The drain of transistor 5 is connected to the source of a PMOS-type power transistor 8. The drain of transistor 8 is connected to column C. A switch 9, controlled by a control signal φC, is capable of connecting the gate of transistor 8 to bias voltage VPOL, for example, when control signal φC is high, and to the gate of transistor 6 when control signal φC is low. When signal φC is low, transistor 8 is on and column C charges to reach voltage VCOL. When line L and column C are activated, line and column control signals φL and φC are respectively high and low, light-emitting diode d is on, and the current flowing through the diode is equal to luminance current ILUM. The circuit for grounding column C when control signal φC is high is not shown.
For column control circuit CC to operate as described previously, it is necessary for voltage VPOL to be sufficiently high for the copying of voltage ILUM to be correct. Bias voltage VPOL is equal to the sum of drain-source voltage Vds2 of transistor 2, of voltage Vd across light-emitting diode d, of source-drain voltage Vsd8 of transistor 8, and of source-drain voltage Vsd5 of transistor 5.
When the copying of current ILUM is correct, transistor 5 is in saturation state and voltage Vsd5 is at least equal to source-drain voltage Vsd4 of transistor 4. A correct copying of the current in the duplication branch thus causes bias voltage VPOL to be at least equal to the previously-mentioned sum when the current that it conducts is equal to luminance current ILUM. If bias voltage VPOL is too low, the current flowing through light-emitting diode d is smaller than current ILUM and the diode luminance is insufficient.
Luminance current ILUM provided by current source 7 may generally vary according to the luminance desired for the screen. When luminance current ILUM increases, source-drain voltage Vsd4 of diode-assembled transistor 4 increases and voltage Vd of light-emitting diode d also increases. As a result, bias voltage VPOL must be high enough for transistor 5 to be in saturation whatever the luminance current.
However, for electric power saving reasons, bias voltage VPOL is desired to be decreased, which then enables reducing voltage Vligne of the line control circuits.
There exist control circuits which have a fixed bias voltage VPOL determined according to the maximum desired luminance current ILUM. The disadvantage of such circuits is their high electric power consumption.
There exist other control circuits for which bias voltage VPOL varies according to the desired luminance current ILUM. If current ILUM is low, voltage VPOL is low, and conversely. However, it is necessary to provide a security margin to take into account the aging of the screen light-emitting diodes. Indeed, for an equal current in light-emitting diode d, voltage Vd across the diode increases along time. For the same luminance, corresponding to a given luminance current, the necessary minimum bias voltage VPOL thus progressively increases with time. The obtained power savings for these circuits are thus not optimal.